Efficient 4-Bit Encoder Design with Memristor Technology and SAPON Integration

Abstract

This study displays three different encoder setups: CMOS, Memristor, and Pseudo NMOS. Digital logic gate designs that use memristors provide an alternative to the present IC architecture. This computing architecture will be among the upcoming ones. The poly silicon gate of an NMOS transistor can be used to build memristors, making MRL gates simple to fabricate. The encoder's design makes use of four bits. When comparing the recommended 4-bit encoder with memristor logic to one with CMOS logic and pseudo-N MOS logic, the former requires less power. This paper also presents a 4-bit encoder design that combines SAPON methodology with memristor technology, aiming for low-power optimization and increased efficiency. Memristors' dynamic resistance and non-volatile memory enhance encoding performance, minimizing energy consumption and ensuring strategic power optimization. Experimental results demonstrate its potential for efficiency and power conservation.