Multi-Bit Error Resilient FPGA Cram with Minimum TTD

Abstract

In harsh environments such as space, radiation and charged particles cause Single-Event and Multi-bit Effects, faults occurring randomly on any electronic component. These must be mitigated to ensure device functionality. Modern mitigation methods, such as triple modular redundancy, are very effective against Single Event Transients (SETs), but incur a minimum of 3× cost in area. Single-Event Upsets (SEUs) affect sequential elements and are regularly repaired using memory scrubbing. Scrubbing is a slow serial process, going through every memory word looking for errors to repair. It involves a non-negligible Time to Detect (TTD) before repair, during which other events can occur and compromise the system. Field Programmable Gate Arrays (FPGAs) rely heavily on sequential elements to store their configuration; thus, FPGA’s SEU detection time is critical to ensuring design integrity in harsh conditions. It is required a robust error correction code (ECC) to protect electronic devices from MCUs. The proposed work describes the conception, implementation and evaluation of new algorithm using matrix code for the detection and correction of multiple errors in FPGA configuration memories. The combined architecture with multiple bit segment with parity bits helps in locating and correcting double-triple bit errors. The proposed Method allows asynchronous MEU detection and replaces scrubbing variable time to detect with a fixed TTD. The IMECCC based on Matrix code reduces FPGA’s TTD compared to existing method.