Implementation of a Static Contention Free Characteristics Differential Flip Flop Using GDI in Clock Gating Technique

Abstract

This paper introduces the design of a differential flip-flop featuring static contention- free characteristics, achieved through the implementation of a GDI-AND arrangement within a clock gating technique. The proposed approach aims to enhance the reliability and performance of flip-flops in digital circuits, particularly in applications demanding low-voltage and low-power operation. By incorporating a GDI-AND structure in the clock gating technique, contention issues are minimized, ensuring stable and efficient operation. The abstract outlines the design methodology, emphasizing the integration of static contention-free attributes and the innovative use of clock gating with a GDI- AND. This research contributes valuable insights into advancing the design of differential flip-flops, offering improved reliability and efficiency in modern digital systems.