Review of Vedic Multiplier Architectures for High Performance FFT Processing

Abstract

One of the basic arithmetic operations in digital systems is multiplication, especially in applications such as spectral analysis, image processing, and signal processing. Multiplier performance directly impacts factors like speed, power efficiency, and system throughput. Traditional architectures such as array multipliers, Wallace tree multipliers, and Booth multipliers improve either speed or area efficiency but fail to optimize both simultaneously.Vedic mathematics offers an alternative approach through sutra-based computational techniques such as Urdhva-Tiryakbhyam and Nikhilam, which enable high parallelism, reduced propagation delay, and modular scalability. This review paper consolidates research on 16-bit Vedic multiplier designs and analyzes their integration in FFT (Fast Fourier Transform) processors. It examines conventional, modified, and hybrid Booth–Vedic architectures implemented on FPGA and ASIC platforms.

Comparative results show that hybrid Booth–Vedic designs achieve up to 89% reduction in area and 72% improvement in Area–Delay Product (ADP) compared to conventional designs. The paper also discusses architectural trade-offs, implementation challenges, and future research directions for advancing Vedic arithmetic hardware in next-generation digital systems.