Multi-Bit Error Resilient FPGA Cram with Minimum TTD. International Research Journal on Advanced Engineering Hub (IRJAEH), [S. l.], v. 2, n. 06, p. 1551–1557, 2024. DOI: 10.47392/IRJAEH.2024.0212. Disponível em: https://irjaeh.com/index.php/journal/article/view/247.. Acesso em: 29 jun. 2024.